b9949 low voltage pecl clock distribution buffer preliminary international microcircuits, inc. 525 los coches st. rev 1.0 5/15/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 1 of 5 http://www.imicorp.com product features 160mhz clock support 2.5v or 3.3v output capability lvpecl or lvcmos/lvttl clock input lvcmos/lvttl compatible inputs 15 clock outputs: drive up to 30 clock lines 1x and 1/2x configurable outputs output tri-state control 350ps maximum output-to-output skew pin compatible with mpc949 52-pin tqfp package block diagram figure 1 description the b9949 is a low voltage clock distribution buffer with the capability to select either a differential lvpecl or lvcmos/lvttl compatible input clocks. these clock sources can be used to provide for test clocks as well as the primary system clocks. all other control inputs are lvcmos/lvttl compatible. the 15 outputs are 2.5v or 3.3v lvcmos or lvttl compatible and can drive two series terminated 50 w transmission lines. with this capability the b9949 has an effective fan-out of 1:30. the b9949 is capable of generating 1x and 1/2x signals from a 1x source. these signals are generated and retimed internally to ensure minimal skew between the 1x and 1/2x signals. sel(a:d) inputs allow flexibility in selecting the ratio of 1x to1/2x outputs. the b9949 outputs can also be tri-stated via mr/oe# input. when mr/oe# is set high, it resets the internal flip-flops and tri-states the outputs. pin configuration mr/oe# tclk_sel vdd tclk0 tclk1 pecl_clk pecl_clk# pclk_sel dsela dselb dselc dseld vss nc vddc qd4 vss qd3 vddc qd2 vss qd1 vddc qd0 vss nc nc vddc qb2 vss qb1 vddc qb0 vss vss qa1 vddc qa0 vss nc vss qc0 vddc qc1 vss qc2 vddc qc3 vss vss qd5 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 b9949 2 qa0:1 3 qb0:2 4 qc0:3 6 qd0:5 0 1 0 1 0 1 0 1 0 1 0 1 /1 /2 r tclk0 (lvttl) tclk_sel tclk1 (lvttl) pecl_clk pecl_clk# pclk_sel dsela dselb dselc dseld mr/oe#
b9949 low voltage pecl clock distribution buffer preliminary international microcircuits, inc. 525 los coches st. rev 1.0 5/15/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 2 of 5 http://www.imicorp.com pin description pin name pwr i/o description 6 pecl_clk i, pd pecl input clock. 7 pecl_clk# i, pu pecl input clock. 4, 5 tclk(0,1) i, pu external reference/test clock input. 49, 51 qa(1,0) vddc o clock outputs. 42, 44, 46 qb(2:0) vddc o clock outputs. 31, 33, 35, 37 qc(3:0) vddc o clock outputs. 16, 18, 20, 22, 24, 28 qd(5:0) vddc o clock outputs. 9, 10, 11, 12 dsel(a:d) i, pd divider select inputs. when high, selects ? 1 input divider. when low, selects ? 2 input divider. 2 tclk_sel i, pd tclk select input. when low, tclk0 clock is selected and when high tclk1 is selected. 8 pclk_sel i, pd pecl select input. when high, pecl clock is selected and when low tclk(0,1) is selected 1 mr_oe# i, pd output enable input. when asserted low, the outputs are enabled and when asserted high, internal flip-flops are reset and the outputs are tri-stated. 17, 21, 25, 32, 36, 41, 45, 50 vddc 2.5v or 3.3v power supply for output clock buffers. 3 vdd 3.3v power supply 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 vss common ground 14, 26, 27, 39, 40, nc not connected pd = internal pull-down, pu = internal pull-up.
b9949 low voltage pecl clock distribution buffer preliminary international microcircuits, inc. 525 los coches st. rev 1.0 5/15/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 3 of 5 http://www.imicorp.com maximum ratings maximum input voltage relative to vss: vss - 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: -65 c to + 150 c operating temperature: 0 c to +70 c maximum esd protection 2kv maximum power supply: 5.5v maximum input current: 20ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) b9949 low voltage pecl clock distribution buffer preliminary international microcircuits, inc. 525 los coches st. rev 1.0 5/15/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 4 of 5 http://www.imicorp.com ac parameters 1 symbol parameter min typ max units conditions fmax maximum input frequency 2 160 mhz pecl_clk to q delay 2 4.0 - 8.0 tpd ttl_clk to q delay 2 4.4 - 8.9 ns foutdc output duty cycle 2,3 tcycle/2 C 1 tcycle/2 + 1 ns measured at vddc/2 tpzl, tpzh output enable time (all outputs) 2 10 ns tplz, tphz output disable time (all outputs) 2 10 ns tskew output-to-output skew 2,4 350 ps tr / tf tclk input rise / fall 3.0 ns tr / tf output clocks rise / fall time 4 0.10 1.0 ns 0.8v to 2.0v vddc = 2.5v +/- 5% or 3.3v +/- 5%, vdd = 3.3v +/- 5%, ta = 0 c to +70 c note 1: parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with loaded outputs. note 2: outputs driving 50 w transmission lines. note 3: 50% input duty cycle. note 4: outputs loaded with 30pf each
b9949 low voltage pecl clock distribution buffer preliminary international microcircuits, inc. 525 los coches st. rev 1.0 5/15/2000 milpitas, ca 95035, usa tel: 408-263-6300, fax 408-263-6571 page 5 of 5 http://www.imicorp.com package drawing and dimensions (52 tqfp) 52 pin tqfp outline dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a2 0.037 - 0.041 0.95 - 1.05 d - 0.472 - - 12.00 - d 1 - 0.394 - - 10.00 - b 0.009 - 0.015 0.22 - 0.38 e 0.026 bsc 0.65 bsc l 0.018 - 0.030 0.45 - 0.75 ordering information part number package type production flow B9949AA 52 pin tqfp commercial, 0 c to +70 c note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi B9949AA date code, lot # B9949AA package a = tqfp revision imi device number d d 1 a 2 b e 10 a l a 1
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